The present invention relates to digital communication systems and is more particularly concerned with a method and apparatus for recovering binary data which has been encoded within a serial waveform. The invention is particularly suited for the recovery of so-called "teletext" data encoded into certain lines of a standard television broadcast signal.
The general problem of accurately reconstructing binary data encoded within a serial waveform is one which has been faced and solved in many ways over the years. These waveforms may be generically categorized as self-clocking and non-self-clocking. A self-clocking signal carries "extra" information embedded within its waveform which may be used to stimulate and synchronize a circuit to extract the data portion of the waveform. Non-self-clocking waveforms, on the other hand, carry only the data itself; clocking information must be derived indirectly in this case.
Examples of self-clocking waveforms include FM, MFM, M2FM and (2,7)RLL codes widely used in the magnetic media industry, and Manchester encoding commonly used in local area networks. The implementation of these schemes is exemplified by the Manchester scheme, shown in FIG. 1. In Manchester decoding, the received state of a particular encoded binary bit is determined by the direction of a waveform transition at the center of a "bit cell." A positive going transition indicates a "1", and a negative going transition indicates a "0". The guaranteed presence of a transition within each bit cell constitutes the extra information required for self-clocking, in that the presence of this transition can be used to synchronize a clocking circuit. However, in order to represent consecutive identical bits (i.e., 00 or 11), a space for an extra transition must be reserved between the "center" transitions, during which the waveform can return to its previous state. The space required for this transition effectively reduces the available bandwidth of the channel carrying the Manchester data to one half of its potential. Some of the other cited schemes reduce the bandwidth impact by varying amounts by reducing the density of required transitions within groupings of adjacent bits.
The most common and simplest non-self-clocked scheme is Non-Return-to-Zero, or NRZ. In this scheme, shown in FIG. 2, the binary state of a particular bit is determined by the signal level at the nominal center of a bit cell. Transitions between signal levels occur at bit cell boundaries; there is, in general, no guarantee of any particular density of such transitions.
Data extraction from such signals relies on the short-to-medium term accuracy and stability of transmission and reception oscillators. If both transmitter and receiver are initially synchronized and use relatively accurate oscillators for their basis timing, then they can remain synchronized for relatively long strings of bit cells. The required initial synchronism is commonly achieved by a training pattern transmitted at the beginning of a message (an arbitrarily long stream of data bits). This pattern, called a "preamble" or "clock run-in", typically contains a maximal transition density, such as alternating 1's and 0's. The receiver analyzes the clock run-in sequence to determine the optimal sampling point for each bit cell; this is nominally the center of the bit cell. The receiver then "locks" to this sample point and relies on the stability of its oscillator to assure that each succeeding bit cell is sampled near its optimal sampling point. Clearly, the maximum message length is a function of the accuracy and stability of the receiving and transmitting timing oscillators.
Several approaches to extracting data from selfclocked or non-self-clocked serial data streams are known in the art, including phase-locked loops, high speed digital sampling, clock phase adjustment, and data phase adjustment.
A phase-locked loop circuit involves a variable frequency oscillator which is controlled so as to maintain a constant phase relationship between the received signal and the output of the oscillator. The desired frequency and phase are established in the oscillator during the preamble portion of a received message. Some circuits continue to adjust the oscillator during the data portion of the message. The disadvantages of phase-locked loops include the need for mixed analog and digital circuitry, significant sensitivity to operating conditions, and sometimes difficult design trade-offs between capture range, lock acquisition time and allowable phase jitter, particularly when handling NRZ waveforms.
A second approach is to use high frequency sampling of the serial waveform. The receiver's oscillator, typically crystal controlled, operates at a multiple "n" of the received data rate. A typical value of n would be at least eight. Sampling of the data stream produces a sequence of n values per bit period. Circuits associated with the oscillator determine the location of bit periods by detecting transitions between consecutive sampled values (1.fwdarw.0 or 0.fwdarw.1). Such transitions mark either the center or the boundary of a bit cell, depending on the coding used and the data pattern transmitted during the preamble. Upon detection of a preamble transition, a counter which is clocked by the high frequency oscillator is forced to a preset value and then allowed to free run. The counter is designed to implement a division ratio of n, and recycles once per bit period. Thus, after the initial transition is detected, the counting sequence is locked into the received serial waveform and may be used to determine appropriate times to extract a data bit. Some systems continue to adjust the counting sequence based on the counter value when transitions are detected. This allows tracking of long term frequency drift between transmitter and receiver oscillators.
The major disadvantage of the sampling approach is that it requires a very high speed oscillator to achieve acceptable resolution when sampling high speed serial data. For instance, to handle 5.7 Megabit/second data with n=8, the sampling oscillator must operate at 45.6 MHz. Clock speeds in this range or higher cause significant practical problems, including limitations on the logic families that may be used, excessive power dissipation, and substantial electromagnetic emissions. Even at this rate, the sampling resolution of 8 clocks per bit is marginal for precise data recovery. Sampling multiples of 12 or more are clearly preferable, but may be untenable due to the high oscillator frequency required.
The third approach mentioned, clock phase adjustment, is less commonly used, but is quite powerful. It is exemplified by the Intel 82C501AD serial Ethernet interface chip. In this scheme, the phase of a receiver oscillator free-running at the basic bit frequency is adjusted through a set of discrete values to correspond to the incoming serial waveform. This may be done by passing the oscillator output into a delay line with multiple delay tap points. Based on the position of clock transitions within the delay line when a preamble data transition occurs, the circuit could establish a delay tap to use to obtain a clocking signal for a data sampling flip flop. The circuit might also provide for continual refinement of the selected tap point, based on further data transitions. Resolution available with this technique is limited only by the maximum practical number of discrete phase steps (or delay line taps). Its principal disadvantage is the difficulty of implementing precision delay lines in digital integrated circuits.
The fourth approach, and the one used in the present invention, is data phase adjustment. This approach somewhat resembles the clock phase adjustment scheme described above, except that it uses a delay line to provide multiple discrete values of data phase rather than clock phase. Data phase adjustment provides the functional equivalent of very high speed digital sampling without the requirement for a correspondingly high oscillator frequency and admits of a certain degree of tolerance in the delay line.
The data phase adjustment approach is known from U.S. Pat. Nos. 3,908,084 and 4,012,598--both issued to Wiley and incorporated herein by reference. Briefly, as the approach is preferably implemented in the present invention, the incoming data signal is fed to a multi-tap delay line, respective outputs of which are connected to corresponding inputs of a clocked register, the outputs of which are in turn connected to corresponding inputs of a second register. At any point in time, the collective outputs of the two registers constitute multiple samples of the incoming data signal over a span of two clock pulses, with the individual samples representing the value of the incoming signal at points separated in time by the delay increment between successive taps of the delay line. The collective register outputs are examined for the clock run-in or preamble to determine which output indicates the occurrence of a transition. Depending on the output which marks the transition, an output corresponding to the desired sampling point is determined and used for data extraction.
Both of the aforementioned Wiley patents implement the data phase adjustment approach on the assumption that the nominal bit cell center point as determined during the clock run-in or preamble is the optimal sampling point for accurate data recovery. In practice, however, this assumption often does not hold.
Numerous forms of distortion may affect the data waveform between its generation and its reception. For instance, in the teletext application the data is modulated onto an RF carrier along with the remainder of the television signal. This signal may be routed over satellite links, and through multiple modulations and demodulations before being delivered to the final receiver through aerial or cable distribution systems. Each of these steps causes distortions of the final received waveform, the most significant of which is group delay distortion.
Group delay distortion is caused by nonlinear phase delay characteristics in components such as amplifiers and filters in the distribution path. The effect is to cause high and low frequencies to be delayed by different amounts. Since the spectrum of the waveform includes many frequencies, the effect of the varying delay is to distort the received signal. More particularly, the run-in contains principally the highest frequency components of any portion of the message, since alternating 1's and 0's are the fastest possible transitions in an NRZ code. Other portions of the message contain considerably more of lower frequency components. The effect of group delay distortion is thus to perturb the data transitions between NRZ bit cells away from their nominal positions (as determined from the clock run-in) in a data dependent (frequency dependent) way. As a result, transitions between low and high signal levels may move from their nominal positions depending on the data content of the signal. Thus, the nominal center of bit cells derived from the clock run-in phase ordinarily is not the optimal sampling point for achieving maximum recovery accuracy.